1. Field of the Invention
The present invention concerns a method of forming trench isolation having a polishing step and a method of manufacturing a semiconductor device having a polishing step. The present invention can be applied to the formation of trench isolation (trench type inter-device separation) in various kinds of electronic materials, a method of manufacturing various kinds of semiconductor devices braving trench isolation, as well as a method of manufacturing various kinds of semiconductor devices having a recess burying step and a subsequent flattening and polishing step. Further, it can be utilized as a method of manufacturing a semiconductor device having a polishing step including a step of burying recesses defined with a plurality of protrusion patterns (that is, defined between each of protrusion patterns) by a burying material and a step of flattening the burying material formed on the protrusion patterns.
2. Description of the Prior Art
Polishing techniques have a wide application of use and it can be utilized, for example, for flattening unevenness resulting in a substrate such as a semiconductor substrate during manufacturing a semiconductor device (refer, for example, to Japanese Patent Laid Open sho 63-39835).
On the other hand, capacitances of devices have been increased in the field of semiconductor devices and various kinds of techniques have been developed in order to increase the capacitance while minimizing chip area to as small as possible and, for example, a multi-layered wiring technique is indispensable therefor. In the multi-layered wiring technique, it is extremely important to flatten the underlying substrate in order to prevent disconnection of the multi-layered wiring. This is because unevenness on the underlying substrate, if any, will lead to occurrence of wire disconnection at a step caused by the unevenness (so-called step disconnection). In order to flatten the underlying substrate satisfactorily, flattening at the initial stage is important.
For attaining the above-mentioned object, there has been considered, for example, a flat trench isolation. Trench isolation is a technique for inter-device isolation by burying an insulator in trenches formed on a semiconductor substrate and it is advantageous for higher degree integration since fine trenches can be formed. However, after burying, i.e. filling, the trenches, it is necessary to remove protrusions of the burying material deposited at the portions other than in the trenches for attaining a flattened surface. The trench can be formed as a recess between two protrusion patterns but, when a burying material is buried, i.e. filled, in the recess (trench), since the burying material is also deposited on the protrusion patterns other than the trench to form a protruding portion, it has to be flattened. A method as shown in FIGS. 11a-11c is known as a method of forming a flat trench isolation.
In this method, as shown in FIG. 11(a), a thin silicon oxide film 2 and a thin silicone nitride film 3 are formed on a semiconductor substrate 1, then trenches 41, 42 and 43 are formed by etching using a photolithographic step and, subsequently, an inner wall oxide film, that is, the silicon oxide layer 2 is formed by oxidation to provide a semiconductor substrate.
Then, as shown in FIG. 11(b), a burying material 5 is deposited in the trenches 41-43 by a deposition means, for example, CVD to obtain a structure as shown in the figure. In this case, the burying material 5 is deposited to a large thickness also on the portions other than in the trenches 42-43 to result in protrusions 51.
Accordingly, as shown in FIG. 11(c), the protrusions 51 are removed by polishing to flatten the surface by polishing. In a case where silicone oxide is used as the burying material 5, a silicon nitride film 3 having a polishing rate lower than that of silicon dioxide may be used for instance as a stopper layer for polishing.
Such a method is applied, in addition to the trench isolation process, also to other processes for forming flat interlayer insulation films such as formation of a trench capacitor accompanying trench burying, formation of trench contact (trench plug) or formation of a layer by a blanket W-CVD process.
However, in a case where a wide recessed region (1) and a narrow protruding region (2) are formed as shown in FIG. 12(a). When polishing is applied directly after burying the trenches 41-43, the burying material 52 (SiO.sub.2 or the like) that is not removed completely remains in the central portion of the burying material 5 on the wide protruding region (1), and SiO.sub.2 or the like which is the burying material 52 is raised to result in occurrence of particles when the stopper layer 2 (for example) Si.sub.3 N.sub.4 is removed by hot phosphoric acid in the succeeding step.
As a countermeasure for overcoming the problem, for instance, IBM has presented the following technique in IEDM in 1989 (IEDM 89, pp 61-64). That is, as shown in FIG. 13(a), a block resist 31 is formed in the recess of CVD-SiO.sub.2 as the burying material 5, on which a resist coating film 3 is formed which is then etched back. Thus, a structure as shown in FIG. 13(b) is obtained. Then, it is flattened by polishing to obtain a flattened structure as shown in FIG. 13(c). However, in this method, if a patterning for the block resist is displaced to form a resist out of the recess as shown by reference numeral 31' in FIG. 13(d), no sufficient flatness can be obtained even if a resist coating film 3' is formed, so that the burying material 5 does not become flat as shown in FIG. 13(e) and, as a result, it is difficult to flatten by means of polishing.
In addition, there is also the following problem. That is, the flattening technique by polishing involves a problem that the extent of polishing depends on the underlying pattern and sometimes it results in unevenness. Description will now be made to the problem with reference to FIG. 14.
In FIG. 14, trenches 41-43 are formed as recesses between each of protrusion patterns 61-64. The protrusion patterns 61-64 function as a stopper during polishing. As shown in FIG. 14, the density of the protrusion pattern 61 is small or sparse in the portion A of the figure in which the protrusion pattern 61 is present. In the portion B shown in the figure in which the protrusion patterns 62-64 are present, a ratio of the protrusion patterns per unit area (the area ratio of the protrusion patterns) is great and, accordingly, the density of the protrusion pattern is large or dense. In the illustrated embodiment, since silicon nitride or the like is used as a polishing stopper layer and is formed on the protrusion patterns 61-64, the area of the stopper layer 3 per unit area is small and, accordingly, the density thereof is sparse in the illustrated portion A. On the other hand, since the area of the stopper layer 3 per unit area is large, the density of the polishing stopper 3 is dense in the illustrated portion B shown in the figure. If there is unevenness of the ratio of the polishing stopper layer 3 (which exists for each of the protrusion patterns 61-64), polishing tends to become uneven.
For instance, in a peripheral circuit, if the area ratio per unit area of a protrusion pattern present at the periphery that functions as a polishing stopper layer is low (for example, in a case of the region A in FIG. 14), since polishing pressure is concentrated during polishing on the protrusion pattern (stopper layer), the polishing rate is increased, so that mere selection of the ratio of the protrusion pattern (stopper layer) is insufficient and the isolation pattern 61 is worn off as shown in FIG. 14(b) so that it no longer has its intended effect as the stopper layer. As a result, the region A is concaved and a uniform and satisfactory flattening can not be attained as shown in FIG. 14(b).
Accordingly, there is a demand for a technique capable of attaining satisfactory flattening by polishing also in a case where the distribution of the polishing stopper layer shows unevenness (for instance, in a case where there is an unevenness for the density of protrusion patterns and, accordingly, there is an unevenness in the ratio of the polishing stopper layer) and also for a portion in which the area ratio is low, that is, a portion of a circuit pattern in which the portion that functions as the polishing stopper is sparse.